The present invention relates to charge coupled devices (CCDs) for use in image collection, storage and transfer, in general, and more particularly, to a CCD image detector including a buffer area array separate from an image area array and a storage area array, the buffer area array being controlled independently of the image and storage area arrays to transfer its charge contents to a read out register of the CCD, and a method of operating the same.
Charge coupled devices or CCDs are arrays of semiconductor gates formed on a substrate of an integrated circuit or chip. The gates of the CCD are operative to individually collect, store and transfer charge. When used in image applications, the charge collected and stored in each gate of the array represents a picture element or pixel of an image. A typical CCD detector used for image applications is shown in the diagram of FIG. 1 and includes an image collection area 10, an image storage area 12, and a register 14 for reading out serially the pixel charges of an image one line at a time. Each of the aforementioned two areas 10 and 12 may include an array of 512×512 CCD gates, i.e. 512 lines or rows of 512 gates per row, for example. The readout register 14 includes a line of CCD gates and operates as a shift register shifting out serially the charge contents or image pixel information of a line of the collected image. Gates of the image area 10 may be operated by clock signals 16 to transfer in parallel the charge contents of the gates of one row to another vertically downward in the direction of the arrow 18. Similarly, gates of the storage area 12 are operated by clock signals 20 to transfer in parallel the charge contents of the gates of one row to another vertically downward. And, the gates of the horizontal or readout register 14 are operated by the clock signal 22 to shift out serially from right to left the charge contents of its gates over a signal line 24.
In operation, an image detector CCD gate array may be initially purged of all charge contents, then an image is collected in the form of charges in the individual gates of the image array during a predetermined integration period which may be on the order of 100 to 250 milliseconds, for example. Thereafter, the clock signals 16 and 20 operate together to transfer the current charge contents of the gates of the image area 10 to the gates of the storage area 12 line by line. This transfer process may take on the order of 512 clock pulses of approximately 3 microseconds each, for example. Once the charges representing the pixels of the collected image are stored in the storage area 12, the clock signal 20 may continue to shift the charge contents of the gates of the storage area 12 to the readout register 14 line by line which will take considerably longer because after each new line of charge contents is transferred to the readout register 14, the clock signal 22 clocks out the charge contents (pixel information) serially which may take 512 clock pulses of on the order of 1 microsecond each, for example. So, there will be a delay of 512 microseconds between each line transfer of 512 line transfers of the storage area 12 for readout purposes.
While the foregoing described example used specific values for integration and transfer times, it is understood that these times are application dependent and may change from one application to another. Also, there are other possible methods of clocking a CCD. For example, in some image systems, there is no separate purge cycle to define the start of an integration period. Rather, a frame transfer defines the start of integration which occurs simultaneously with burst/readout cycles.
In band transfer applications of CCD detectors, only one or more bands of adjacent rows of image information or charge content need be read out from the CCD. For example, if a band of rows is 16 rows and there are six mutually exclusive bands, then the storage area 12 may be operated by the clock signal 20 to burst through the rows thereof at a rate of 1–3 microsecond per row until the first band of rows is stored in a like number of rows adjacent the read our register 14. Thereafter, the storage area 12 may be operated to clock each row of the first band into the read out register 14 with a delay of 512 microseconds per row, for example. Once the rows of the first band are clocked out of the CCD, then the storage area 12 may be operated to burst until the second band of rows is stored in the rows adjacent read out register 14 and the process repeated for the remaining five designated bands. In this case, the transfer and readout speed of the CCD is improved by a factor of at least five since the storage area 12 is clocked slowly only approximately 102 times and rapidly clocked for the remainder of lines.
When these CCD detectors are used in an environment unprotected from radiation, like in space and in some cases, in nuclear environments, for example, high energy proton and neutron radiation may penetrate the CCD array and cause phosphorous vacancy (p-v) traps in one or more gates of the CCD where unwanted charge in the form of electrons may be stored. This trapped charge may be released in an exponential manner that can be characterized by a temperature dependent release time constant τR which may be on the order of 270 microseconds at 0° C., for example. Since the p-v capture time is very short, the CTE, which is a measure of how much charge is transferred, is independent of how the CCD is clocked. Where the p-v trapped charge is released does depend on the manner in which the CCD is clocked to transfer charge from gate to gate in relation to τR. In other words, if the CCD is clocked at a rapid rate like during frame transfers from the image area to the storage area or during bursting from one band to another, for example, so that the each clock pulse is much shorter than τR, then the charge released from the trap will be spread uniformly over the charge contents of many gates and may easily be removed by thresholding, for example. On the other hand, if the CCD is clocked slowly, like when data is being readout through register 14, for example, so that the clock period or delay is longer than τR, then most of the trapped charge will be released to the next charge content being shifted through the gate. This condition will result in a shift in the image centroid in a direction opposite to the transfer direction and a degradation of the high frequency modulation transfer function (MTF) of the CCD detector. The shift in the centroid position will increase linearly with the number of slow (period>τR) clock pulses required to read out the image.
The present invention improves the likelihood of trapped charge in one or more gates of the CCD being released over a multiplicity of charge contents (pixel information) during a charge transfer process, thus, reducing the risk of occurrence of the aforementioned problems.